• Home
  • Tutorials
  • Interviews
  • Info Seed
  • Forums
  • Projects
  • Links
  • Contact Us
Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
COMBINATIONAL CKT
INTRODUCTION
ADDER
FULL ADDER(FA)
FA using HAs
BINARY ADDER
SERIAL ADDER
PARALLEL ADDER
CARRY LOOK AHEAD ADDER (CLA)
QUESTION (BCD to Excess-3 using ADDER)
SUBTRACTORS
FULL SUBTRACTOR
FS using HSs
MORE QUESTIONS
SEQUENTIAL CIRCUITS
TIMING CIRCUITS

 

Parallel Subtractor:

All inputs are feed simultaneously.

Borrow-propagate subtractor:

Similar to the case of adder we can have the circuit as follow:

Similar to the adder case we have the delay for n-bit subtractor as (2n+1) Δ and so for 16 bit subtractor as 33Δ.

Borrow look ahead subtractor:

Hence to reduce this time delay we employ another method to design the subtractor same as the case of adder.

 

So we have the following equations:

B2=G1+P1*B1

B3=G2+P2*B2= G2 + P2*(G1+P1*B1)=G2+G1*P2 + P1*P2*B1

B4=G3+P3*B3=G3 + P3*(G2+G1*P2 + P1*P2*B1)= G3+G2*P3 + G1*P2*P3 + B1*P1*P2*P3

B5=G4+P4*B4= G4 + P4*(G3+G2*P3 + G1*P2*P3 + B1*P1*P2*P3)

= G4 + G3*P4 + G2*P3*P4 + G1*P2*P3*P4 + B1*P1*P2*P3*P4

Similar to the adder circuit we have the delay for borrow look ahead subtractor is for a 16-bit adder as

= Δ + 2Δ + 2Δ + 2Δ + 2Δ + 3Δ = 12Δ which is also illustrated below:

And delay is reduced by factor of 3.

 

previous next
| Copyright © 2009 exploreroots- All Rights Reserved | Disclaimer |